~ruther/verilog-riscv-semestral-project

ref: 732301c9f816051cb1b7937d011d3b21d10f68c2 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes
057ee98b — Rutherther 2 years ago 
chore: add generated bin, obj gitignore files
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore