~ruther/verilog-riscv-semestral-project (732301c9f816051cb1b7937d011d3b21d10f68c2): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

732301c9 — Rutherther chore: move inital sp to 1020 1 year, 5 months ago

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.envrc

10 bytes

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.gitignore

90 bytes

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Makefile

2.2 KiB

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flake.lock

1.5 KiB

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flake.nix

1.3 KiB

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programs/

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src/

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testbench/

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