~ruther/verilog-riscv-semestral-project

ref: 732301c9f816051cb1b7937d011d3b21d10f68c2 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes
732301c9 — Rutherther chore: move inital sp to 1020 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat