~ruther/verilog-riscv-semestral-project

ref: 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f verilog-riscv-semestral-project/src/stages d--------- 
docs: better document the stage code, organize it better

chore: import cpu types in stages

feat: add forwarding signal for better debugging

feat: implement pipeline