~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB 
fix: do not set subtract for non-R instructions

fix: make immediates sign extended

fix: do not use immediate in alu src for SB

feat(decoder): implement memory mask, conditional jumps

feat: add instruction decoder
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