~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 66fd5da9a15539865c07f3516a5e396674a2bf16

~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

b7fa590c — Rutherther 2 years ago

chore: add cpu types for various sources

Better orientation by name instead of
number