~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 1.1 KiB 
chore: extend memory

tests: add register dump, printing

feat: add support for loading and saving ram from disk

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

fix: offset ram by bytes, not bits

feat: implement sb, sh, lb, lh support via masking

feat: add basic ram, alu, and register file
Do not follow this link