~ruther/verilog-riscv-semestral-project

ref: 280332ea3bcdd58544d3b1606eedd54fda0f1611 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes 
chore: move inital sp to 1020

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

feat: add basic testing programs
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