~ruther/verilog-riscv-semestral-project

ref: 280332ea3bcdd58544d3b1606eedd54fda0f1611 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
280332ea — Rutherther fix: make Makefile work with memory load, write files 1 year, 5 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop
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