~ruther/verilog-riscv-semestral-project

ref: 0d5d1a1fc04a21df2c7cf81ce969e9c02c125901 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.9 KiB
66d14163 — Rutherther 2 years ago
feat: move jumping to execute stage
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better
89310129 — Rutherther 2 years ago
feat: implement pipeline
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
7ad51766 — Rutherther 2 years ago
fix: remove duplicit instruction and pc in cpu
8f631f51 — Rutherther 2 years ago
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
82d9e44f — Rutherther 2 years ago
feat: add cpu top level entity