~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.9 KiB 
feat: implement sb, sh, lb, lh support via masking

fix: do not set subtract for non-R instructions

fix: make immediates sign extended

fix: do not use immediate in alu src for SB

feat(decoder): implement memory mask, conditional jumps

feat: add instruction decoder
Do not follow this link