fix: csn was rising too soon for divisors > 2

fix: short last sck pulse on slower clock

fix: divisors list had excess element

fix: assumptions about synthesizable code

fix: masterslave component inputs tx_valid, rx_ready were outs

feat: add lsbfirst support

fix: support other divisors than 2

fix: multiple issues in design

- setting lost rx data at correct time
- clearing lost rx data on start so the value is determined
- resolving pulses on stuff that depended on zero signal in ctrl
- allowing next tx right after one ended (crucial for divisor = 2)

fix: master_ctrl_rst_n shou be used, not master_ctrl_rst, start_clock is split

feat: implement masterslave spi switch peripheral