fix: short last sck pulse on slower clock

fix: master didn't go to invalid data when data are read on first cycle of ready

fix: rx, tx disabling

fix: prevent pulses on tx_ready_o, rx_block assertion when rx is ready

fix: support other divisors than 2

fix: multiple issues in design

- setting lost rx data at correct time
- clearing lost rx data on start so the value is determined
- resolving pulses on stuff that depended on zero signal in ctrl
- allowing next tx right after one ended (crucial for divisor = 2)

feat: implement masterslave spi switch peripheral

feat: implement initial hdl_spi