chore: update vunit run.py

tests: wait for half period after stop condition in model

chore: add questa to flake

tests: update address detector to use new bus mod

tests: i2c bus model

docs: add presentation

tests: add message handler for i2c bus model

tests: add packages for communication with i2c bus model

fix: ssd1306 logic

fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

docs: finish documentation

feat: split ssd1306 counter to logic entity

fix: use synced sda, scl for master, slave entities

docs: styling

docs: add basic documentation

chore: update flake inputs, add docs dev env

tests: fix address generator done test

feat: store address, rw in address generator or detector

fix: move to bus busy on arbitration err or start condition

feat: add libraries to vunit