tests: wait for half period after stop condition in model
1 files changed, 1 insertions(+), 1 deletions(-) M tb/i2c/model/i2c_bus_mod.vhd
M tb/i2c/model/i2c_bus_mod.vhd => tb/i2c/model/i2c_bus_mod.vhd +1 -1
@@ 336,7 336,7 @@ begin -- architecture behav error(logger, "Timed out when waiting for sda rising edge to generate a stop condition!"); end if; - wait for s_scl_period / 4; + wait for s_scl_period / 2; info(logger, "Stop condition generated.");