fix: count to 9, make i2c frequency 10 MHz

feat: simplify bcd counter

fix: make sure clock divider has 50 % duty cycle

docs: add basic README documentation

tests: diable no_check taking long

fix: full_on skips indices

fix: many changes

chore: update constraints for master ssd1306

fix: issues on master

fix: issues in master logic

tests: advanced master tests

tests: add basic master testbench

fix: some stuff

fix: logic fixes master state

feat: prepare i2c slave tb model

tests: add address generator testbench

fix: address generator minor issues

tests: add startstop condition generator testbench

fix: start stop condition generator behavior

fix: make sure scl changed after delay