fix: start stop condition generator behavior

fix: make sure scl changed after delay

fix: scl generator minor mistakes

feat: add master top entity

feat: add master state entity

feat: add scl generator

feat: add address generator

feat: add start, stop condition generator

feat: add waiting output to slave

feat: add done fields to tx, rx

chore: get rid of "pulse" from scl names

feat: handle errors in slave state

Moves logic of error handling to slave_state
from tx entity.

feat: add unexpected_sda tx signal

feat: add clear_buffer input to tx

fix: make slave work

feat: add slave top

feat: handle ack in rx, tx

feat(tx): remove unnecessary bit index

feat: add stateful sda, scl switch

chore: use process(all) for combinational processes