M src/i2c/slave.vhd => src/i2c/slave.vhd +3 -0
@@ 156,6 156,9 @@ begin -- architecture a1
scl_stretch_o => tx_scl_stretch,
sda_i => sda_i,
sda_enable_o => tx_sda_enable,
+ unexpected_sda_o => open, -- ignore in the slave, nothing to do?
+ -- TODO output an error if unexpected
+ -- level when transmitting
ready_o => tx_ready_o,
valid_i => tx_valid_i,
write_data_i => tx_data_i);
M src/i2c/tx.vhd => src/i2c/tx.vhd +5 -3
@@ 24,10 24,11 @@ entity tx is
clk_i : in std_logic;
rst_in : in std_logic;
start_write_i : in std_logic;
- ss_condition_i : in std_logic; -- Reset rx circuitry
- clear_buffer_i : in std_logic;
+ ss_condition_i : in std_logic; -- Reset rx circuitry
+ clear_buffer_i : in std_logic;
- expect_ack_i : in std_logic;
+ expect_ack_i : in std_logic;
+ unexpected_sda_o : out std_logic;
err_noack_o : out std_logic;
scl_rising_pulse_i : in std_logic;
@@ 80,6 81,7 @@ begin -- architecture a1
scl_stretch_o <= '1' when curr_state = WAITING_FOR_DATA else '0';
ready_o <= ready and not curr_err_noack;
sda_enable_o <= not tx_buffer(8) when curr_state = SENDING else '0';
+ unexpected_sda_o <= '1' when curr_state = SENDING and sda_i /= tx_buffer(8) else '0';
err_noack_o <= curr_err_noack;
ready <= '0' when curr_tx_buffers_filled(curr_saving_buffer_index) = '1' or curr_err_noack = '1' else '1';
M tb/i2c/tx_tb.vhd => tb/i2c/tx_tb.vhd +3 -0
@@ 29,6 29,8 @@ architecture a1 of tx_tb is
signal write_data : std_logic_vector(7 downto 0);
signal scl_stretch : std_logic;
+ signal unexpected_sda : std_logic;
+
signal err_noack : std_logic;
signal validate_sda_stable_when_scl_high : std_logic := '0';
@@ 133,6 135,7 @@ begin -- architecture a1
scl_stretch_o => scl_stretch,
scl_rising_pulse_i => scl_rising_pulse,
scl_falling_delayed_i => scl_falling_pulse,
+ unexpected_sda_o => unexpected_sda,
sda_enable_o => sda_enable,
sda_i => sda,
ready_o => ready,