4 files changed, 15 insertions(+), 7 deletions(-)

M src/i2c/slave.vhd
M src/i2c/slave_state.vhd
M src/i2c/tx.vhd
M tb/i2c/slave_tb.vhd

@@ 23,11 23,12 @@ entity slave is
     rx_stretch_i : in std_logic;
 
     -- tx
-    tx_ready_o   : out std_logic;       -- Transmitter ready for new data
-    tx_valid_i   : in std_logic;        -- Are data in tx_data valid? Should be
+    tx_ready_o        : out std_logic;  -- Transmitter ready for new data
+    tx_valid_i        : in  std_logic;  -- Are data in tx_data valid? Should be
                                         -- a pulse for one cycle only
-    tx_data_i    : in std_logic_vector(7 downto 0);  -- Data to transmit
-    tx_stretch_i : in std_logic;
+    tx_data_i         : in  std_logic_vector(7 downto 0);  -- Data to transmit
+    tx_stretch_i      : in  std_logic;
+    tx_clear_buffer_i : in  std_logic;
 
     -- errors
     err_noack_o  : out std_logic;


@@ 141,10 142,11 @@ begin  -- architecture a1
       confirm_read_i        => rx_confirm_i);
 
   -- tx
-  tx: entity work.tx
+  tx : entity work.tx
     port map (
       clk_i                 => clk_i,
       rst_in                => rst_in,
+      clear_buffer_i        => tx_clear_buffer_i,
       start_write_i         => transmitting,
       expect_ack_i          => expect_ack_i,
       err_noack_o           => err_noack_o,

@@ 30,7 30,7 @@ architecture a1 of i2c_slave_state is
     TRANSMITTING,       -- we are transmitting data
     BUS_BUSY);          -- bus is taken, different slave communicating
 
-  signal curr_state : slave_state;
+  signal curr_state : slave_state := BUS_FREE;
   signal next_state : slave_state;
 
   signal communicating_with_master : std_logic;

@@ 25,6 25,7 @@ entity tx is
     rst_in              : in  std_logic;
     start_write_i       : in  std_logic;
     ss_condition_i      : in std_logic;    -- Reset rx circuitry
+    clear_buffer_i      : in std_logic;
 
     expect_ack_i        : in std_logic;
     err_noack_o         : out std_logic;


@@ 178,7 179,7 @@ begin  -- architecture a1
   set_regs: process (clk_i) is
   begin  -- process set_next
     if rising_edge(clk_i) then          -- rising clock edge
-      if rst_in = '0' or ss_condition_i = '1' then  -- synchronous reset (active low)
+      if rst_in = '0' or clear_buffer_i = '1' then  -- synchronous reset (active low)
         curr_state <= IDLE;
         curr_tx_buffers <= (others => (others => '0'));
         curr_tx_buffer_index <= 0;


@@ 186,6 187,10 @@ begin  -- architecture a1
         curr_saving_buffer_index <= 0;
         curr_scl <= '1';                -- assume 1 (the default, no one transmitting)
         curr_err_noack <= '0';
+      elsif ss_condition_i = '1' then
+        curr_state <= IDLE;
+        curr_scl <= '1';                -- assume 1 (the default, no one transmitting)
+        curr_err_noack <= '0';
       else
         curr_state <= next_state;
         curr_tx_buffers <= next_tx_buffers;

@@ 274,6 274,7 @@ begin  -- architecture tb
       tx_valid_i     => tx_valid,
       tx_data_i      => tx_data,
       tx_stretch_i   => '0',
+      tx_clear_buffer_i => '0',
 
       err_noack_o    => err_noack,
       rw_o           => rw,