3 files changed, 3 insertions(+), 2 deletions(-)

M src/i2c/address_detector.vhd
M src/i2c/rx.vhd
M tb/i2c/rx_tb.vhd

@@ 49,7 49,7 @@ begin  -- architecture a1
 
   mismatch <= '1' when curr_index <= 6 and address_i(6 - curr_index) /= sda_i and scl_pulse_i = '1' else '0';
 
-  set_next_state: process (start_i, curr_state, mismatch, scl_pulse_i) is
+  set_next_state: process (all) is
   begin  -- process set_next_state
     next_state <= curr_state;
 

@@ 81,7 81,7 @@ begin  -- architecture a1
   -- SAVING_STRETCHING -> SAVING_STRETCHING when data not read yet
   -- SAVING_STRETCHING -> RECEIVING when data read
 
-  set_next_state: process(curr_state, start_read_i, scl_pulse_i, confirm_read_i) is
+  set_next_state: process(all) is
   begin  -- process set_next_state
     next_state <= curr_state;
 

@@ 77,6 77,7 @@ begin  -- architecture a1
     port map (
       clk_i          => clk,
       rst_in         => rst_n,
+      ss_condition_i => '0',
       start_read_i   => start_read,
       scl_pulse_i    => scl_rising_pulse,
       sda_i          => sda,