tests: update address detector to use new bus mod

tests: i2c bus model

tests: add message handler for i2c bus model

tests: add packages for communication with i2c bus model

tests: fix address generator done test

feat: store address, rw in address generator or detector

fix: move to bus busy on arbitration err or start condition

fix: issues on master

tests: advanced master tests

tests: add basic master testbench

fix: some stuff

feat: prepare i2c slave tb model

tests: add address generator testbench

tests: add startstop condition generator testbench

fix: make sure scl changed after delay

tests: add test for scl generator

chore: get rid of "pulse" from scl names

feat: handle errors in slave state

Moves logic of error handling to slave_state
from tx entity.

feat: add unexpected_sda tx signal

refactor: get rid of sda, scl overrides, drive sda, scl directly