@@ 21,14 21,12 @@ architecture tb of slave_tb is
constant CLK_PERIOD : time := 10 ns;
signal rst_n : std_logic := '0';
- signal sda_override : std_logic := '0';
signal slave_sda_enable : std_logic;
signal slave_sda : std_logic;
signal address : std_logic_vector(6 downto 0);
signal not_scl : std_logic;
- signal scl_override : std_logic := '0';
signal slave_scl_enable : std_logic;
signal slave_scl : std_logic;
@@ 51,9 49,6 @@ begin -- architecture tb
sda <= 'H';
scl <= 'H';
- sda <= '0' when sda_override = '1' else 'Z';
- scl <= '0' when scl_override = '1' else 'Z';
-
sda <= '0' when slave_sda_enable = '1' else 'Z';
scl <= '0' when slave_scl_enable = '1' else 'Z';
@@ 107,44 102,44 @@ begin -- architecture tb
if run("simple_read") then
address <= "1100001";
- i2c_master_start("1100001", '1', scl_override, sda_override);
+ i2c_master_start("1100001", '1', scl, sda);
tx_write_data("11010100", tx_data, tx_valid);
tx_write_data("00110011", tx_data, tx_valid);
- i2c_master_receive("11010100", scl_override, sda_override);
+ i2c_master_receive("11010100", scl, sda);
check_equal(rw, '1');
check_equal(dev_busy, '1');
- i2c_master_receive("00110011", scl_override, sda_override);
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_receive("00110011", scl, sda);
+ i2c_master_stop(scl, sda);
wait until falling_edge(clk);
wait until falling_edge(clk);
check_equal(dev_busy, '0');
check_equal(bus_busy, '0');
elsif run("simple_write") then
address <= "1100000";
- i2c_master_start("1100000", '0', scl_override, sda_override);
- i2c_master_transmit("11010100", scl_override, sda_override);
+ i2c_master_start("1100000", '0', scl, sda);
+ i2c_master_transmit("11010100", scl, sda);
check_equal(rw, '0');
check_equal(dev_busy, '1');
rx_read_data("11010100", rx_confirm);
- i2c_master_transmit("11001100", scl_override, sda_override);
+ i2c_master_transmit("11001100", scl, sda);
rx_read_data("11001100", rx_confirm);
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
wait until falling_edge(clk);
wait until falling_edge(clk);
check_equal(dev_busy, '0');
check_equal(bus_busy, '0');
elsif run("different_address") then
address <= "1111000";
- i2c_master_start("1100000", '0', scl_override, sda_override, exp_ack => '0');
- i2c_master_transmit("11010100", scl_override, sda_override, exp_ack => '0');
+ i2c_master_start("1100000", '0', scl, sda, exp_ack => '0');
+ i2c_master_transmit("11010100", scl, sda, exp_ack => '0');
check_equal(dev_busy, '0');
check_equal(bus_busy, '1');
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
wait until falling_edge(clk);
wait until falling_edge(clk);
@@ 153,19 148,19 @@ begin -- architecture tb
elsif run("read_noack") then
address <= "1100001";
- i2c_master_start("1100001", '1', scl_override, sda_override);
+ i2c_master_start("1100001", '1', scl, sda);
tx_write_data("11010100", tx_data, tx_valid);
check_equal(err_noack, '0');
- i2c_master_receive("11010100", scl_override, sda_override, ack => '0');
+ i2c_master_receive("11010100", scl, sda, ack => '0');
check_equal(rw, '1');
check_equal(dev_busy, '1');
check_equal(err_noack, '1');
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
wait until falling_edge(clk);
wait until falling_edge(clk);
@@ 173,24 168,24 @@ begin -- architecture tb
check_equal(bus_busy, '0');
elsif run("write_read") then
address <= "1100000";
- i2c_master_start("1100000", '0', scl_override, sda_override);
- i2c_master_transmit("11010100", scl_override, sda_override);
+ i2c_master_start("1100000", '0', scl, sda);
+ i2c_master_transmit("11010100", scl, sda);
check_equal(rw, '0');
check_equal(dev_busy, '1');
rx_read_data("11010100", rx_confirm);
- i2c_master_start("1100000", '1', scl_override, sda_override);
+ i2c_master_start("1100000", '1', scl, sda);
tx_write_data("11010100", tx_data, tx_valid);
- i2c_master_receive("11010100", scl_override, sda_override);
+ i2c_master_receive("11010100", scl, sda);
check_equal(rw, '1');
check_equal(dev_busy, '1');
tx_write_data("00001111", tx_data, tx_valid);
- i2c_master_receive("00001111", scl_override, sda_override);
+ i2c_master_receive("00001111", scl, sda);
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
wait until falling_edge(clk);
wait until falling_edge(clk);
check_equal(dev_busy, '0');
@@ 11,28 11,28 @@ use work.tb_i2c_pkg.all;
package tb_i2c_master_pkg is
procedure i2c_master_stop (
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic);
+ signal scl : inout std_logic;
+ signal sda : inout std_logic);
procedure i2c_master_transmit (
constant data : in std_logic_vector(7 downto 0);
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant stop_condition : in std_logic := '0';
constant exp_ack : in std_logic := '1');
procedure i2c_master_receive (
constant exp_data : in std_logic_vector(7 downto 0);
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant ack : in std_logic := '1';
constant stop_condition : in std_logic := '0');
procedure i2c_master_start (
constant address : in std_logic_vector(6 downto 0);
constant rw : in std_logic;
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant exp_ack : in std_logic := '1');
end package tb_i2c_master_pkg;
@@ 40,40 40,39 @@ end package tb_i2c_master_pkg;
package body tb_i2c_master_pkg is
procedure i2c_master_stop (
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic) is
+ signal scl : inout std_logic;
+ signal sda : inout std_logic) is
begin -- procedure stop_tx
- scl_fall(scl_override);
- sda_fall(sda_override);
- scl_rise(scl_override);
+ scl_fall(scl);
+ sda_fall(sda);
+ scl_rise(scl);
-- stop condition
- sda_rise(sda_override, '0');
+ sda_rise(sda, '0');
end procedure i2c_master_stop;
procedure i2c_master_transmit (
constant data : in std_logic_vector(7 downto 0);
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant stop_condition : in std_logic := '0';
constant exp_ack : in std_logic := '1') is
begin -- procedure transmit
- check_equal(scl_override, '0', "Cannot start sending when scl is not in default state (1).", failure);
check_equal(scl, 'H', "Cannot start sending when scl is not in default state (1). Seems like the slave is clock stretching. This is not supported by transmit since data have to be supplied or read.", failure);
- scl_fall(scl_override);
+ scl_fall(scl);
-- data
for i in 7 downto 0 loop
- sda_override <= not data(i);
- scl_pulse(scl_override);
+ sda <= '0' when data(i) = '0' else 'Z';
+ scl_pulse(scl);
end loop; -- i
- sda_override <= '0';
- scl_rise(scl_override);
+ sda <= 'Z';
+ scl_rise(scl);
if exp_ack = '1' then
check_equal(sda, '0', "No acknowledge");
elsif exp_ack = '0' then
@@ 83,52 82,51 @@ package body tb_i2c_master_pkg is
if stop_condition = '1' then
if sda = '0' then
-- keep sda low
- sda_override <= '1';
+ sda <= '0';
end if;
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
end if;
end procedure i2c_master_transmit;
procedure i2c_master_receive (
constant exp_data : in std_logic_vector(7 downto 0);
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant ack : in std_logic := '1';
constant stop_condition : in std_logic := '0') is
begin -- procedure transmit
- check_equal(scl_override, '0', "Cannot start receiving when scl is not in default state (1).", failure);
check_equal(scl, 'H', "Cannot start receiving when scl is not in default state (1). Seems like the slave is clock stretching. This is not supported by transmit since data have to be supplied or read.", failure);
- scl_fall(scl_override);
- sda_override <= '0';
+ scl_fall(scl);
+ sda <= 'Z';
-- data
for i in 7 downto 0 loop
- scl_rise(scl_override);
+ scl_rise(scl);
if exp_data(i) = '1' then
check(sda = '1' or sda = 'H', result("Received data (sda) not as expected."));
else
check(sda = '0' or sda = 'L', result("Received data (sda) not as expected."));
end if;
- scl_fall(scl_override);
+ scl_fall(scl);
end loop; -- i
if ack = '1' then
- sda_override <= '1';
+ sda <= '0';
end if;
- scl_rise(scl_override);
+ scl_rise(scl);
if stop_condition = '1' then
if sda = '0' then
-- keep sda low
- sda_override <= '1';
+ sda <= 'Z';
end if;
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
end if;
end procedure i2c_master_receive;
@@ 136,29 134,29 @@ package body tb_i2c_master_pkg is
procedure i2c_master_start (
constant address : in std_logic_vector(6 downto 0);
constant rw : in std_logic;
- signal scl_override : inout std_logic;
- signal sda_override : inout std_logic;
+ signal scl : inout std_logic;
+ signal sda : inout std_logic;
constant exp_ack : in std_logic := '1') is
begin
if scl = 'H' and sda = '0' then
- scl_fall(scl_override);
+ scl_fall(scl);
end if;
if sda = '0' then
- sda_rise(sda_override);
+ sda_rise(sda);
end if;
if scl = '0' then
- scl_rise(scl_override);
+ scl_rise(scl);
end if;
check_equal(sda, 'H', "Cannot start sending when sda is not in default state (1).", failure);
check_equal(scl, 'H', "Cannot start sending when scl is not in default state (1).", failure);
-- start condition
- sda_fall(sda_override, '0');
+ sda_fall(sda, '0');
- i2c_master_transmit(address & rw, scl_override, sda_override, stop_condition => '0', exp_ack => exp_ack);
+ i2c_master_transmit(address & rw, scl, sda, stop_condition => '0', exp_ack => exp_ack);
end procedure i2c_master_start;
@@ 27,7 27,6 @@ architecture tb of counter_tb is
signal rst_n : std_logic := '0';
signal rst : std_logic;
- signal scl_override, sda_override : std_logic := '0';
signal not_scl : std_logic;
signal err_noack : std_logic;
@@ 53,8 52,6 @@ begin -- architecture tb
sda <= 'H';
scl <= 'H';
- sda <= '0' when sda_override = '1' else 'Z';
- scl <= '0' when scl_override = '1' else 'Z';
not_scl <= not scl;
clk <= not clk after CLK_PERIOD / 2;
@@ 72,17 69,17 @@ begin -- architecture tb
while test_suite loop
if run("wrapping_counting") then
- i2c_master_start(ADDRESS, '1', scl_override, sda_override);
+ i2c_master_start(ADDRESS, '1', scl, sda);
for i in 0 to 99 loop
- i2c_master_receive(std_logic_vector(to_unsigned(i, 8)), scl_override, sda_override);
+ i2c_master_receive(std_logic_vector(to_unsigned(i, 8)), scl, sda);
end loop; -- i
-- starting over
- i2c_master_receive("00000000", scl_override, sda_override);
- i2c_master_receive("00000001", scl_override, sda_override);
+ i2c_master_receive("00000000", scl, sda);
+ i2c_master_receive("00000001", scl, sda);
- i2c_master_stop(scl_override, sda_override);
+ i2c_master_stop(scl, sda);
end if;
end loop;