fix: make sure clock divider has 50 % duty cycle

fix: full_on skips indices

fix: many changes

fix: issues on master

fix: issues in master logic

fix: some stuff

fix: logic fixes master state

fix: address generator minor issues

fix: start stop condition generator behavior

fix: make sure scl changed after delay

fix: scl generator minor mistakes

feat: add master top entity

feat: synchronize reset in mcu slave tops

feat: add master state entity

feat: add scl generator

feat: add address generator

feat: add start, stop condition generator

feat: add waiting output to slave

feat: add done fields to tx, rx

chore: get rid of "pulse" from scl names