4 files changed, 20 insertions(+), 5 deletions(-)

M src/mcu_slave/counter.vhd
M src/mcu_slave/regs.vhd
M tb/mcu_slave/counter_tb.vhd
M tb/mcu_slave/regs_tb.vhd

@@ 31,6 31,7 @@ architecture a1 of counter is
   signal go_next : std_logic;
 
   signal rst_n : std_logic;
+  signal rst_sync : std_logic;
 
   signal sda, scl : std_logic;
   signal sda_enable, scl_enable : std_logic;


@@ 38,9 39,15 @@ architecture a1 of counter is
   signal tx_valid, tx_ready : std_logic;
   signal tx_data : std_logic_vector(7 downto 0);
 begin
-  rst_n <= not rst_i;
+  rst_n <= not rst_sync;
   rst_on <= rst_n;
 
+  sync_reset: entity utils.metastability_filter
+    port map (
+      clk_i    => clk_i,
+      signal_i => rst_i,
+      signal_o => rst_sync);
+
   next_count <= (curr_count + 1) mod MAX when go_next = '1' else
                 curr_count;
 

@@ 30,6 30,7 @@ architecture a1 of regs is
   signal next_regs : regs_t;
 
   signal rst_n : std_logic;
+  signal rst_sync : std_logic;
 
   signal sda, scl : std_logic;
   signal sda_enable, scl_enable : std_logic;


@@ 53,8 54,15 @@ architecture a1 of regs is
 
   signal rw : std_logic;
 begin
-  rst_n <= not rst_i;
-  rst_on <= not rst_i;
+  rst_n <= not rst_sync;
+  rst_on <= rst_n;
+
+  sync_reset: entity utils.metastability_filter
+    port map (
+      clk_i    => clk_i,
+      signal_i => rst_i,
+      signal_o => rst_sync);
+
   dev_busy_o <= dev_busy;
 
   next_dev_busy <= dev_busy;

@@ 55,7 55,7 @@ begin  -- architecture tb
   not_scl <= not scl;
 
   clk <= not clk after CLK_PERIOD / 2;
-  rst_n <= '1' after 2 * CLK_PERIOD;
+  rst_n <= '1' after 6 * CLK_PERIOD;
   rst <= not rst_n;
 
   -- TODO: allow conditions from master...

@@ 56,7 56,7 @@ begin  -- architecture tb
   not_scl <= not scl;
 
   clk <= not clk after CLK_PERIOD / 2;
-  rst_n <= '1' after 2 * CLK_PERIOD;
+  rst_n <= '1' after 6 * CLK_PERIOD;
   rst <= not rst_n;
 
   -- TODO: allow conditions from master...