~ruther/verilog-riscv-semestral-project (a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7): .gitignore

~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

a6f4c7fc — Rutherther chore: add new files to compilation list 1 year, 6 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/