~ruther/verilog-riscv-semestral-project

ref: 707b5bfcbb7652d77af7da28688aceff0a98892b verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
707b5bfc — Rutherther chore: add makefile for both verilog and c 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd