~ruther/verilog-riscv-semestral-project: .gitignore 707b5bfcbb7652d77af7da28688aceff0a98892b

~ruther/verilog-riscv-semestral-project

ref: 707b5bfcbb7652d77af7da28688aceff0a98892b verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes

65ab00a4 — Rutherther 2 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 2 years ago

chore: add gitignore