~ruther/verilog-riscv-semestral-project (707b5bfcbb7652d77af7da28688aceff0a98892b): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

707b5bfc — Rutherther chore: add makefile for both verilog and c 1 year, 7 months ago

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.envrc

10 bytes

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.gitignore

52 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

d---------

src/

d---------

testbench/

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