~ruther/verilog-riscv-semestral-project (38e84297e0e6abf0ec14d91878d5210792b801bd): tests/official/env/ - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

38e84297 — Rutherther fix: shift left only by 5 bits 2 years ago

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