~ruther/verilog-riscv-semestral-project (30a7f9492e5e15f2d64dded11bc5080af6b54ec5): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

30a7f949 — Rutherther feat: add basic testing programs 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}