~ruther/verilog-riscv-semestral-project (30a7f9492e5e15f2d64dded11bc5080af6b54ec5): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

30a7f949 — Rutherther feat: add basic testing programs 1 year, 7 months ago

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.envrc

10 bytes

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.gitignore

52 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

d---------

programs/

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src/

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testbench/

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