~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
30a7f949 — Rutherther feat: add basic testing programs 2 years ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop