~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 2 years ago 
                                                                                
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SECTIONS
{
  .text.init = 0x0;
}