~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 197 bytes
18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 2 years ago 
                                                                                
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src/cpu_types.sv
src/instruction_decoder.sv
src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv
src/ram.sv
src/cpu.sv
src/file_program_memory.sv

testbench/tb_cpu_program.sv