~ruther/verilog-riscv-semestral-project (057ee98bbecfb8a284b67bef50b04b70ae18e220): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

057ee98b — Rutherther chore: add generated bin, obj gitignore files 1 year, 7 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat