~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/.envrc -rwxr-xr-x 10 bytes
057ee98b — Rutherther chore: add generated bin, obj gitignore files 1 year, 7 months ago
                                                                                
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use flake
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