~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/tests d---------
chore: remove unnecessary executable flags

Closes #4.
feat: move jumping to execute stage
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
chore: add new files to compilation list
docs: add basic documentation
tests: add more custom tests
tests: add register dump, printing
tests: compile only once, copy proram, memory files to correct locations
feat: add support for official tests
tests: add python test environment for custom tests
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