~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rw-r--r-- 3.2 KiB
79c7be5c — Rutherther 2 years ago main
chore: remove unnecessary executable flags

Closes #4.
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
89310129 — Rutherther 2 years ago
feat: implement pipeline
db85fb35 — Rutherther 2 years ago
tests: fix ram and control_unit tests to match newest architecture
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
2929a779 — Rutherther 2 years ago
test: add basic testbenches