~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rw-r--r-- 3.2 KiB 
chore: remove unnecessary executable flags

Closes #4.

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline

tests: fix ram and control_unit tests to match newest architecture

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add basic testbenches
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