~ruther/verilog-riscv-semestral-project: src/file_program_memory.sv feat/misaligned-reads

308a1462 — Rutherther 1 year, 5 months ago

tests: add register dump, printing

51842d38 — Rutherther 1 year, 5 months ago

feat: add support for official tests

ee0204c8 — Rutherther 1 year, 5 months ago

feat: pass program to execute by parameter

938d89a2 — Rutherther 1 year, 5 months ago

refactor: change program mem to file prog mem

64d33d25 — Rutherther 1 year, 5 months ago

feat: add program memory