~ruther/verilog-riscv-semestral-project

ref: feat/misaligned-reads verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 381 bytes
d4e70aa6 — Rutherther 2 years ago
fix: linker file issues, naming of linked file
732301c9 — Rutherther 2 years ago
chore: move inital sp to 1020
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
30a7f949 — Rutherther 2 years ago
feat: add basic testing programs