~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/src d---------
69ced879 — Rutherther 2 years ago 
fix: make rd1, rd2 in register_file regs
e3c95ad3 — Rutherther 2 years ago 
feat: add instruction decoder
51a684d9 — Rutherther 2 years ago 
chore: formatting
8adc02d7 — Rutherther 2 years ago 
feat: add basic ram, alu, and register file