~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/src/stages/decode.sv -rw-r--r-- 4.1 KiB 
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better

feat: add forwarding signal for better debugging

feat: implement pipeline
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