~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/programs d---------
bb32d2dd — Rutherther 2 years ago 
feat: add gcd program for testing
adfdc041 — Rutherther 2 years ago 
feat: add branches.c test
6ce1c838 — Rutherther 2 years ago 
chore: remove gcc generated file
30a7f949 — Rutherther 2 years ago 
feat: add basic testing programs