~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/programs d--------- 
feat: add gcd program for testing

feat: add branches.c test

chore: remove gcc generated file

feat: add basic testing programs
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