~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/programs d---------
bb32d2dd — Rutherther 2 years ago 
feat: add gcd program for testing
adfdc041 — Rutherther 2 years ago 
feat: add branches.c test
6ce1c838 — Rutherther 2 years ago 
chore: remove gcc generated file
30a7f949 — Rutherther 2 years ago 
feat: add basic testing programs