~ruther/verilog-riscv-semestral-project: src/cpu_types.sv e44bfc9ea42a45f5776158e8e51c025f185b4f56

~ruther/verilog-riscv-semestral-project

ref: e44bfc9ea42a45f5776158e8e51c025f185b4f56 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

b7fa590c — Rutherther 1 year, 7 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number