~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/src/file_program_memory.sv -rwxr-xr-x 319 bytes 
tests: add register dump, printing

feat: add support for official tests

feat: pass program to execute by parameter

refactor: change program mem to file prog mem

feat: add program memory
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