~ruther/verilog-riscv-semestral-project

ref: d4e70aa69c3671bba9e02d198267f09cfc493a11 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 4.2 KiB
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
7ad51766 — Rutherther 2 years ago
fix: remove duplicit instruction and pc in cpu
8f631f51 — Rutherther 2 years ago
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
82d9e44f — Rutherther 2 years ago
feat: add cpu top level entity