~ruther/verilog-riscv-semestral-project: programs cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c

~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/programs d---------

6ce1c838 — Rutherther 1 year, 7 months ago

chore: remove gcc generated file

30a7f949 — Rutherther 1 year, 7 months ago

feat: add basic testing programs