~ruther/verilog-riscv-semestral-project: programs 6ce1c83859b56b514f0a4536ddb388cacc77773e

~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/programs d---------

6ce1c838 — Rutherther 1 year, 7 months ago

chore: remove gcc generated file

30a7f949 — Rutherther 1 year, 7 months ago

feat: add basic testing programs